A clock signal is a steady stream of timing pulses that synchronize each and every operation within a data processing system. The clock rate of a computer essentially determines the maximum operating speed of that computer. Computer designers are continually attempting to increase the speed of computers, and thus always desire a faster clock rate.
A problem with merely increasing the clock rate is that the signal generated and transmitted becomes degraded at high frequencies to the extent where the various components within the data processing system are either not able to interpret the clock pulses or erroneously interpret clock signals, resulting in a lack of synchronization within the data processing system. One of these problems is a skewing of the clock signal, which may result in the clocked circuits not responding evenly to the clock signal. A related symptom is the concept of duty cycle. If each pulse of the clock signal is not comprised of substantially a 50% duty cycle, synchronization may be lost.
Complimentary Metal-Oxide Semiconductor ("CMOS") field-effect transistor logic circuitry has become a dominant technology in the production and manufacture of circuitry in data processing systems. Such CMOS transistors offer low power dissipation, but require a minimum level of bias voltage in order to effectively operate. In comparison to bipolar technology, CMOS operates on a square law principal. Bipolar components consume more power than CMOS components. Furthermore, CMOS is voltage dependent while bipolar components are dependent upon current to drive the circuit. CMOS circuits operate on a threshold voltage, which is the voltage that turns a device on. This bias voltage commonly determines the voltage swing of a clock signal produced with such CMOS circuitry. However, this voltage swing limits the clock speed in that the rise time required to transition from the low level to the high voltage level of the clock signal determines how quickly the clock signal can transition from one pulse to the next. In other words, it takes a longer time for the signal to rise and then to fall. A full swing voltage signal also dissipates more power than a low voltage swing signal. Additionally, a full swing signal causes more coupled noise, since noise is proportional to the voltage swing. Furthermore, a full voltage swing signal can cause distortion of the clock pulse width induced by dispersion in the distribution media.
As a result of the foregoing, there is a need in the art for clock generation circuitry that provides a higher frequency clock signal at lower voltage levels within CMOS technology.